Asynchronous circuits operate without a clock. Quasi Delay Insensitive (hereinafter “QDI”) circuits are robust to variable operating conditions, but like any other digital circuits they are susceptible to soft errors. As the circuit feature size decreases, soft error rates increase and become a concern both for logic designers and for operation of real circuits in certain inhospitable environments.
QDI circuits are a class of delay-insensitive asynchronous circuit which are invariant to (and make no assumptions about) the delays of any of the circuit's elements, except to assume that certain fanouts are isochronic forks. Isochronic forks allow signals to travel to two (or more) destinations and only receive an acknowledge signal from one. Isochronic forks are forks in circuit elements such as wires. In an isochronic fork, if the acknowledging target has seen a transition on its branch of the fork, then the transition must have also happened on the other branch (or branches) of the fork as well. There are two types of isochronic forks. An asymmetric isochronic fork only ensures that the signal will reach an acknowledging node on one branch before or at the same time that the signal will arrive at the other node on another branch. A symmetric isochronic fork ensures that the signal will arrive at nodes on both branches at the same time. Symmetrical isochronic forks allow either of the targets to acknowledge the signal. In QDI circuits all forks have to be either isochronic and acknowledged by one of the destinations, or acknowledged by all destinations.
Several QDI microprocessors have been designed by compilation of message passing specifications into guarded commands. An example is the Caltech MiniMIPS processor, the first fully QDI processor, which approached commercial MIPS implementations in performance, and worked over a larger range of supply voltages and temperatures.
During demonstrations, the Caltech researchers loaded a simple program which ran in a tight loop, and which pulsed one of the output lines after each instruction. This output line was connected to an oscilloscope. When a cup of hot coffee was placed on the chip, the pulse rate (the effective “clock rate”) naturally slowed down to adapt to the worsening performance of the heated transistors. When liquid nitrogen was poured on the chip, the instruction rate increased. Additionally, at lower temperatures, the voltage supplied to the chip could be safely increased, which also improved the instruction rate.
In 2004, Epson manufactured the first flexible microprocessor, an 8-bit asynchronous chip. Synchronous flexible processors cannot be built, since bending the material on which a chip is fabricated causes unpredictable variations in the delays of various transistors, violating the timing assumptions inherent in synchronous design. The Epson processor is intended for use in smart cards, whose chips are currently limited in size to those small enough to remain undistorted.
Some of the benefits provided by QDI circuits include: robust handling of metastability of arbiters; lower power consumption due to the fact that no transistor performs transitions unless it is performing useful computation; elimination of distribution of a high-fanout, timing-sensitive clock signal; elimination of assumptions about the manufacturing process that affect timing; circuit speed that responds to changing temperature and voltage conditions rather than being limited to the slowest speed mandated by worst-case assumptions; immunity to transistor-to-transistor variability in the manufacturing process; and reduction in electromagnetic interference (or EMI) caused by clocking circuits.
Prior art error correction methods applied in synchronous circuits include triple modular redundancy with voters. When a soft error occurs, a conventional QDI system may perform incorrectly or halt. There is a need for systems and methods to mitigate the effects of soft errors on circuits of various kinds, including asynchronous circuits.